SoC Design Lead Engineer

Join the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the SOC Lead / Design Engineer responsible for designing complex SOC using ARM architecture. As a SOC Design Engineer with a focus on ARM Ecosystem Components and Architecture, you will work to understand the internal requirements and complexities of our SOC system and architect the SoC. You will help design the SoC RTL, Integrate IPs and define top level logic. You will also work with verification team to make sure that high quality verification is achieved for first pass success of SoC. You will also participate in architecture/product definition through early involvement in the product life-cycle.

Requirements

• Minimum BE/BS degree (Masters preferred) in Electrical/Electronics Engineering/VLSI with 10+ years of practical experience
• Strong fundamentals in digital ASIC design
• Expertise in ARM v8 and v9 specifications and their impact to SoC system architecture
• Multiple project experience with ARM based ecosystem components (A-series ARM Cores, SMMU, GIC, Coresight, NIC and other complex bus interconnects)
• Familiarity with AMBA bus protocols, system memory hierarchy, system debug infrastructure and multi-core SOC designs
• Exposure to ARM platform architecture specifications
• Strong experience with Verilog, SystemVerilog, DC/DC-T based synthesis, constraints development and RTL level checks. Low power methodology knowledge will be a plus.
• Understanding of major SOC interfaces like PCIE, DRAM, Flash, I2C, SSP, UART.
• Capable of working with multiple IP vendors and other teams
• Excellent communication and leadership quality to lead design team

Responsibilities

• Contribute to SoC architecture for a multi-core ARM SOC
• Define SoC micro architecture and design
• Build SoC around key ARM subsystem components and other IPs including various interfaces
• Design of clock-reset architecture and RTL implementation
• Integration of all IPs into SoC
• Work with verification team for complete SoC verification, review test plans
• RTL Simulation and debug
• Synthesis, Lint, CDC checks
• Assist in emulation, FPGA, prototyping effort

Contact email: [email protected]